1. Field
The present disclosure relates to a multi-chip package and a method of manufacturing thereof, and more particularly, to a multi-chip package and a method of manufacturing the same, which can facilitate wire bonding even when an upper chip is larger than a lower chip.
2. Description of the Related Art
Semiconductor packaging technologies are being developed to meet increasing demands for multifunctional, high capacity, and compact semiconductor packages. To achieve this, a system in package (SIP) technology has been proposed to realize a small, slim, multifunctional, high capacity semiconductor package by incorporating a plurality of semiconductor chips or packages into a single semiconductor package
The SIP is divided into two categories: Package on Package and Multi-Chip Package (MCP). The Package on Package is formed by vertically stacking individual semiconductor packages subjected to electrical tests. The MCP is capable of mounting a plurality of semiconductor chips in a single semiconductor package.
When an upper chip is larger than a lower chip in a MCP, several failures may occur during wire bonding of a chip pad located at an overhang portion of the upper chip (not supported by the lower chip). More specifically, since a conventional MCP has no configuration or member for supporting the overhang portion of the upper chip, cracks may be created in the upper chip when a large force is applied during wire bonding. Furthermore, applying a small force during wire bonding may cause an incomplete bond.